Q2 Implementation Details
All logic in the Q2 is implemented using n-channel MOSFETs with resistor pull-ups. Compared to a bipolar logic family like TTL, NMOS is nice because it requires fewer components: an NMOS inverter requires only a single transistor and a single pull-up resistor.
The idea is pretty simple: a voltage present at the gate of the MOSFET exceeding the threshold voltage (Vth) allows current to flow from the drain to the source. The transistor acts as a variable resistor until the gate voltage increases to the drain voltage (Vds) minus Vth, at which point the transistor is completely on (saturated). Since we use NMOS devices, this means that a high voltage at the gate will pull the output to ground. On the other hand, a low voltage at the gate will turn off the transistor, allowing the pull-up resistor to bring the output high.
A complication of discrete NMOS logic is introduced through the use of three-terminal devices where the bulk terminal is tied to the source terminal. This creates a parasitic diode between the drain in the source. The diode doesn't present too many issues, but it can lead to surprises. For instance, to make a pass transistor gate you need two transistors instead of one. Note that when designing an IC you get to tie the bulk to ground instead of the source, which eliminates the diode. Thus it is important to be wary of circuits that come from a VLSI textbook.
The resistor pull-up presents a trade-off between speed and power, where a lower value resistor pull-up will make the gate faster at the expense of more power draw when the output is low. The situation is made worse by the fact that most modern discrete MOSFETs have a rather high gate capacitance (likely because they are made for switching large loads rather than implementing logic), making fast logic tricky to implement without using excessive power.
Although NMOS has a nearly unlimited fanout due to the high impedance between the input and output, the gate capacitance means that as we increase the fanout, the propagation delay increases. For the Q2, we try to use mostly 10k pull-up resistors as a compromise between speed and power. If we assume a load of 50pF and a Vth of 2.5 (pessimistic values for the gate capacitance and threshold voltage of a 2N7002), this gives us a propagation delay of around 347ns and a current draw of 0.5mA at 5V for a fanout of one. As the fanout increases to, for example, 24 to clock the A register, the propagation delay increases to 8.32us just for the last level of logic. If we wanted to clock the Q2 at 100kHz, this would leave us only 1.68us of slack for all other logic. To avoid such issues, we track the fanout and insert 1k resistors instead of 10k resistors in strategic locations, which in this case brings the delay down to 832ns with a draw of 5mA.
Since USB adapters are prevalent and provide an easy 5v power source, the Q2 was designed to use USB for power. In general, this limits the power consumption to be 500mA. It is relatively easy to verify that the Q2 will not draw too much power.
The primary source of power consumption in the Q2 comes from pull-up networks. For simplicity, most of the pull-ups are simply resistors, though some of them have an LED in series to show state. We can easily compute the worse-case power draw by assuming all the pull-up networks are grounded using Ohm's law. The power consumption varies depending on the value of the resistor and the presence of the LED:
- LED (2V drop) with 1k resistors: (5 - 2) / 1000 = 3mA
- 1k resistor: 5 / 1000 = 5mA
- 4.7k resistor: 5 / 4700 = 1.06mA
- 10k resistor: 5 / 10000 = 0.5mA
- 100k resistor: 5 / 100000 = 0.05mA
From this we get 438mA from pull-up networks. This provides an absolute worst-case estimate since we don't expect all gates and LEDs to be drawing power at all times (gates only draw power when the output is low).
We assume the two RAM chips use a total of 20mA and the LCD uses 20mA. So we get a total worst-case draw of 478mA or 2.4 Watts.
The following sections detail the various sections of the Q2.