Publications

Joseph G. Wingbermuehle, Ron K. Cytron, and Roger D. Chamberlain, "Superoptimizing Memory Subsystems for Multiple Objectives," in Proc. of 4th Int'l Workshop on On-chip Memory Hierarchies and Interconnects (OMHI), August 2015.

Joseph G. Wingbermuehle. " Application-Specific Memory Subsystems." PhD dissertation, Washington University, 2015.

Joseph G. Wingbermuehle, Ron K. Cytron, and Roger D. Chamberlain, "Superoptimized Memory Subsystems for Streaming Applications," in Proc. of ACM/SIGDA International Symposium on Field-Programmable Gate Arrays (FPGA), February 2015, pp 126-135.

Joseph G. Wingbermuehle, Ron K. Cytron, and Roger D. Chamberlain, "Superoptimization of Memory Subsystems," in Proc. of ACM SIGPLAN Conference on Languages, Compilers, and Tools for Embedded Systems (LCTES), June 2014, pp 145-154.

Joseph G. Wingbermuehle, Ron K. Cytron, and Roger D. Chamberlain, "Compiling for Power with ScalaPipe," Journal of Systems Architecture, 59(8):615-625, September 2013.

Joseph G. Wingbermuehle, Ron K. Cytron, Roger D. Chamberlain, "Optimization of Application-Specific Memories,"IEEE Computer Architecture Letters, online April 2013.

Joseph G. Wingbermuehle, Roger D. Chamberlain, and Ron K. Cytron, "ScalaPipe: A Streaming Application Generator," in Proc. of Symposium on Application Accelerators in High-Performance Computing (SAAHPC), July 2012.

Joseph M. Lancaster, Joseph G. Wingbermuehle, Jonathan C. Beard, and Roger D. Chamberlain, "Crosssing Boundaries in TimeTrial: Monitoring Communications Across Architecturally Diverse Computing Platforms," in Proc. of Ninth IEEE/IFIP International Conference on Embedded and Ubiquitous Computing (EUC), October 2011, pp. 280-287.

Joseph M. Lancaster, Joseph G. Wingbermuehle, and Roger D. Chamberlain, "Asking for Performance: Exploiting Developer Intuition to Guide Instrumentation with TimeTrial," in Proc. of 13th International Conference on High Performance Computing and Communications (HPCC), September 2011.

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